1. Field of the Invention
The present invention relates to method and apparatus for establishing frame synchronization, and in particular, to method and apparatus for establishing frame synchronization for a high-speed digital signal in a digital signal transmission apparatus.
2. Background of the Invention
Heretofore, a frame synchronous circuit, as shown in FIG. 6, comprises a synchronous word decision device 61, an aperture circuit 62, an inverter 63, a backward protection circuit 64, a forward protection circuit 65, a flip-flop circuit 66, and a frame counter circuit 67.
The synchronous word decision device (hereinafter, this is called a decision device) 61 decides frame synchronization by comparing an SW (sync word), which is added in a frame inputted, with a sync word held in its own circuit. The aperture circuit 62 applies an aperture to an output of the decision device 61. The frame counter circuit 67 estimates a predetermined position of a frame, which will be received subsequently, at the time of applying the aperture in the aperture circuit 62.
The backward protection circuit 64 checks whether a sync word is inserted at a predetermined position of a frame, received subsequently, so as to confirm that the sync word decision is the decision to a real sync word. The forward protection circuit 65 confirms that a sync word is inserted at a predetermined position of a frame so as to confirm the synchronization also after the establishment of synchronization.
Frame data, frame-synchronized in the frame synchronous circuit 6 having the above-described configuration, is converted by a serial-parallel converter (S/P) 7 into parallel digital signals, and is outputted.
As one of methods for securing pull-in, there is the method disclosed in Japanese Patent Application Laid-Open No. 62-122433. That is, in the method described in this specification, there is provided a circuit for providing violation of the transmitted code specifications simultaneously to transmitted codes on specific m (mxe2x89xa61) lines of transmission paths among 1 (1xe2x89xa72) lines of transmission paths for transmitting digital data in parallel. Furthermore, in the receiving side of the m (mxe2x89xa61) lines of transmission paths, a circuit is provided, the circuit detecting the violence of the transmitted code specifications. Moreover, in the same receiving side, means is provided for deciding that a time slot is a specific position in a frame when the number of transmission paths where the violation of the transmitted code specifications is detected is equal to or more than a specific value n (nxe2x89xa6m) in the same time slot. Owing to these circuits and means, protection circuits are omitted or simplified. This method is called a tolerance system.
In addition, in the method disclosed in Japanese Patent Application Laid-Open No. 8-30743, each bit of a received signal is compared with a plural bit of sync word, which comparison means holds by itself, in parallel. Since this comparison is performed for all bits of the received signal, this comparison system is called the open aperture system.
Preliminary decision means outputs a preliminary decision signal to estimation means when the preliminary decision means detects bit discrepancy, whose number is equal to or less than a first predetermined number, from the result of comparison means. With corresponding to the input of the preliminary decision signal, estimation means estimates a signal position, where a sync word will be inserted, in the next frame of a received signal.
Decision means obtains the result of the comparison by the comparison means when a positional signal, that is a received signal estimated by the estimation means, is inputted. Then, the decision means decides that the frame synchronization is established when detecting the bit discrepancy, whose number is equal to or less than a second predetermined number that is different from the first predetermined number, from the result of the comparison. This system for performing comparison with the sync word on the basis of the estimated position by the estimation means is called the narrow aperture system.
The above-described conventional frame synchronous circuit treats a high-speed digital signal that is at nearly 100 Mbps. A device treating this high-speed digital signal is required to have a very short propagation delay characteristic, and should have large capacity of memory and the like. Therefore, the device treating the high-speed digital signal becomes expensive, and it is difficult to get the device.
In the device treating the high-speed digital signal, the higher the speed of the digital signal is, the more the number of switchings per unit time increases, and the power consumption at the time of switching and heat generation due to this power consumption increases. Therefore, cooling becomes necessary due to large ordinary power consumption and heat generation, and hence an apparatus becomes large.
On the other hand, the frame synchronous circuit becomes complicated in many cases and treats a high-speed digital signal before serial-parallel conversion. Therefore, the frame synchronous circuit performs parallel processing by performing the serial-parallel conversion of the high-speed digital signal for improving the above-described problem. Nevertheless, it is necessary to establish frame synchronization before the serial-parallel conversion.
An object of the present invention is to provide method and apparatus for establishing frame synchronization that can minimize the number of devices for treating a high-speed digital signal, without deteriorating frame pull-in time and an erroneous synchronization rate, promote cost reduction of an apparatus and availability of parts, and can decrease power consumption and heat generation of the apparatus.
A frame synchronous circuit according to the present invention is a frame synchronous circuit that receives a high-speed digital transmission signal, where sync words, each composed of plural bit, are periodically inserted, and establishes frame synchronization. Thus, the frame synchronous circuit converts the high-speed digital signal into n (n is a positive integer) lines of parallel digital signals, and establishes the frame synchronization by n synchronous word decision devices on the basis of the parallel digital signals. Furthermore, the frame synchronous circuit performs leading-edge positioning and column change of data in each column according to outputs of the synchronous word decision device.
Another frame synchronous circuit according to the present invention is a frame synchronous circuit that receives a high-speed digital transmission signal, where sync words, each composed of plural bit, are periodically inserted, and establishes frame synchronization. Thus, the frame synchronous circuit comprises: conversion means for converting the high-speed digital signal into n (n is a positive integer) lines of parallel digital signals; n synchronous word decision devices deciding the presence of the frame synchronization so as to establish the frame synchronization on the basis of the parallel digital signals converted in the conversion means; and means for performing leading-edge positioning and column change of data in each column according to outputs of the synchronous word decision devices.
That is, the frame synchronous circuit according to the present invention comprises a serial-parallel converter converting the digital signal into n lines of parallel digital signals, and a frame synchronous circuit performing the frame synchronization after the serial-parallel conversion in the serial-parallel converter.
The frame synchronous circuit has n synchronous word decision devices, and function for checking whether a sync word is inserted at a predetermined position of a frame subsequently received so as to confirm that the sync word decision is a decision to a real sync word (a backward protection function), and a function for confirming that a sync word is inserted at a predetermined position of a frame so as to confirm synchronization also after the establishment of synchronization (forward protection function).
In addition, the frame synchronous circuit comprises means for deciding after the establishment of synchronization, into what kind of sync word an apparent sync word changes, and means for performing the leading-edge positioning and column change of data in each column according to the decision.
Owing to this, a circuit treating the high-speed digital signal becomes only the serial-parallel converter having simple circuit configuration. Therefore, since the frame synchronous circuit having complicated circuit configuration in many cases treats low-speed digital signals that are at the 1/n speed of the high-speed digital signal, it is possible to limit devices, treating the high-speed digital signal, to a minimum.
Here, with depending on distribution of sync words to each column due to the uncertainty of the serial-parallel converter, the apparent sync words change in n kinds. Against this, the frame synchronous circuit has n synchronous word decision devices corresponding to the n kinds of changes of the sync words, and performs sync word decision by making the n synchronous word decision devices operate in parallel.
In addition, the frame synchronous circuit has a function for checking whether a sync word is inserted at a predetermined position of a frame subsequently received so as to confirm that the sync word decision is a decision to a real sync word (a backward protection function), and a function for confirming that a sync word is inserted at a predetermined position of a frame so as to confirm synchronization also after the establishment of synchronization (forward protection function).
In addition, so as to correct the uncertainty of the serial-parallel converter, the frame synchronous circuit performs leading-edge positioning and column change of data in each column through means for deciding after the establishment of synchronization into what kind of sync word the apparent sync word changes according to the result of the decision.
Since the above-described frame synchronous circuit has n synchronous word decision devices, this circuit has a probability of causing erroneous synchronization that is n times higher than that of a conventional frame synchronous circuit having only one synchronous word decision device. Similarly, when synchronization becomes out of step, a probability of not deciding out-of-step synchronization in forward protective operation increases n-fold. Therefore, by deciding after the establishment of synchronization into what kind of sync word the apparent sync word changes, the frame synchronous circuit disables the synchronous word decision devices not corresponding to the apparent sync word to output signals.
Owing to this, it is possible to enhance the decision accuracy of the out-of-step synchronization at the time of the erroneous synchronization and out-of-step synchronization to those in the conventional technology. In consequence, it becomes possible to shorten the pull-in time and to prevent erroneous synchronization.
In addition, since the above-described frame synchronous circuit has n synchronous word decision devices, a probability of causing the erroneous synchronization increases n-fold as many as that in the conventional frame synchronous circuit having only one synchronous word decision device. For this reason, the frame synchronous circuit decides at the first sync word decision into what kind of sync word an apparent sync word changes. Then, the frame synchronous circuit disables the synchronous word decision devices not corresponding to the change of the apparent sync word to output signals when checking whether a sync word is inserted at a predetermined position of a frame subsequently received according to the decision.
Owing to this, only one synchronous word decision device operates in the backward protective operation, and hence it is possible to enhance the probability of synchronization decision to the probability in the conventional technology. In consequence, it becomes possible to shorten the pull-in time and to prevent erroneous synchronization.
Furthermore, the above-described frame synchronous circuit disables the synchronous word decision devices, not corresponding to the change of the apparent sync word, to output signals after the establishment of synchronization with the means for deciding into what kind of sync word the apparent sync word changes. Owing to this, it becomes possible to shorten the pull-in time and to prevent erroneous synchronization.